Set of Design Tools

At this time a set of design tools [Fig. 1) was in place that allowed the designer to create relatively large circuits.

The set contains three editors for entry of data. ED is a general-purpose text editor. ICS is a graphics editor used for the design of masks. DRAW is also a graphical editor but is used for schematic data entry rather than entering mask data. Both DRAW and ICS are described in other articles in this issue.

Fig. 1 also shows the various simulators. SUPREM is a process-level simulator that lets the user determine levels of impurity doping concentration as a function of processing variables such as the temperature of the diffusion furnaces. HP-SPICE is a very accurate circuit simulator that can determine voltage and current values with respect to time. Transistors are modeled by analytical expressions for current and charge storage. MOTIS-C is a simplified circuit simulator thai uses data in a table to represent the transistors. TECAP is used to generate models tor MOTIS-C and HP-SPICE. Logic-level simulation is done by TESTAID-1C. Instead of voltage and current levels, its results are in terms of logic levels.

The three electrical simulators HP-SPICE, MOTIS-C, and

DRAW Schematic Editor

TESTAtD-IC Logic Simulator

MOTIS-C Timing Simulator

HP-SPICE Circuit Simulator

TECAP

Characterisation System

HP-SUPHEM Process Simulator

Functional Simulator {not completed)

TESTAtD-IC Logic Simulator

MOTIS-C Timing Simulator

HP-SPICE Circuit Simulator

TECAP

Characterisation System

HP-SUPHEM Process Simulator

Schematic Comparator

(not completed!

SMASH Data Formatter

Topology Extraction

SMASH Data Formatter

Design Rule Check

Mask Modification

IGS Artwork Editor

TEST A ID-IC provides range of capabilities differing in accuracy oi results, size of circuits that can be simulated, and computational requirements. A 10,000-gate circuit can be evaluated in a few minutes with TESTAIU-tC till a 1(>-bit minicomputer, whereas a similar analysis with MOTIS-C requires hours on the Amdahl 47II-VB computer system.

Various methods of artwork verification are also shown in Fig. 1. Tilt; design-rule-checkiug program (PRC) is used to determine the conformance of a design lo the IC process' geometrical requirements. These may include widths, spacious. enclosure clislanr.es and areas. Another verification tool is EXTRACT which creates an electrical schematic from the mask artwork. The schematic can he input to any of the simulators. Although extracted at a transistor level, a program exists tor conversion of this data to the higher level required by the logic simulator. This method of determining whether the artwork meets electrical requirements by simulation has been used at HP. However, a more direel method of verification is desirable. This would involve comparing the extracted schematic with the designer's original intent, as inpul by DRAW. At present this program, COMPARE, is not complete.

Two other programs are listed in Tig. 1. The SMASH program is used to convert artwork data in to a form suitable for use bj the photolithography equipment used to create the processing masks. Mask Modification is a program used to make minor geometrical modifications tn the artwork data before final processing.

These design aids are currently used at Hewlett-Packard. They provide a solution to many of today's IC design problems and support many different design methodologies. Unfortunately none of the design methodologies is guaranteed to produce a good circuit.

Continue reading here: Problems of Current Tools

Was this article helpful?

0 0