Plotter Servo Electronics Contained on a Single IC

by Clement C. Lo

The new X-Y plotter technology described in the accompanying article allows the designer to reduce the complexity and cost associated with the servo control electronics of an electromechanical device Hewlett-Packard Laboratories built numerous prototypes that established the relationship between the digital control circuitry and the mechanism. To achieve me objectives of low cost, small size, low power consumption and high reliability, all of the required digital servo control electronics except the high-current motor drivers were integrated into one NMOS integrated circuit

The basic plotter servo system tor one axis (Fig. i) consists of a host processor, the servo controller IC. motor drivers and a dc motor with a quadrature encoder mounted on the shaft The servo logic can he divided Into five major sections, t Arithmetic logic unit (ALU) to perlorm the summing and error-keeping functions (Fig 2a).

2 Read-only memory (ROM) which stores the predetermined velocity profile of a given electromechanical system

3 Decoding logic to decode nformatlon sent by !he host processor or the quadrature encoder signals.

4. Velocity estimation ¡ogle

INC DEC

_ ^

Host

Motor

Processor

Saturation

Servo

Overflow

Power Supply

Pulse

Unipolar Motar Driver dc Motor with Encoder

Quadrature Signals

Fig. 1. Block diagram of servo control system lor one axis of a low-mass, low-inertia pfaffer One IC contains all of the digital servo control electronics, greatly simplifying the overall system design

5. Pulse-width modulation logic.

The architecture of the NMOS servo controller (Fig. 2b) is in many ways a refinement of the initial servo designs However the total Integration of the whole servo control system Into one iow-

x2 x4

ERR + 1

Yes

ERR M

Burst Select Decode

Velocity

Decode and

-4—

ROM

(TPWM)

Pulse-Width

Modulator

T ▼

T

Motor Saturation Pulse Sign lb}

Motor Saturation Pulse Sign

Fig, 2. (a) Instruction flowchart for ALU used in servo controller IC (b) Architecture of digital servo control system This system is fabricated on a single NMOS IC.

powe* nteg rated c:*c j>; ca-sd for new techniques i both logic and circuit design

Post'or-ng commands are in the form or iNCrement or QECre-men; ~he host processor comr-ands the servo cortro ler .*. th fNC. DEC and the burst select inputs (it2, *4) The direction of motor rotation is determined by either INC or DEC The number of steps the motor will rotate upon each inc or dec command is determined by the iogtc states of ihe burst select inputs They provide a multiplication factor of i. 2. 4, or 6 Tne servo controller implements the position error summing, velocity feedback summing and error amplification function by using an eight-bit ALU The velocity decoder obtains tne velocity by measunng the time between the shaft encoder quadrature state changes and comparing it to a velocity lookup table stored In an on-chip ROM The amount of ROM space required for the enure dynamic range ¡s reduced from 512 bytes to 64 bytes through a novel autorange technique.

The servo controller sends two warning signals back to the host

LJKJ JLrlO

Insmicilon ROM fwcoc*

Insmicilon ROM fwcoc*

SoiitlQfl Error r «riMhM

SoiitlQfl Error

Fig. 3. Microphatograph of servo controller IC with various functional areas identified This chip is 3 48 mm wide ana 3.3 mm high, roughly this size: I

processor Under normal operation DOT tne '"□tor saturation and servo overflow outputs should be ai a og:c zero state When the output of the pulse-width modulation log^c reaches a 90% duty cycle, themotor saturation ou(put wilt go to a ogic one state. Once it reaches a 100% duty cycle, the servo cannot accelerate the motor any taster and will fall behind This wilt eventually cause the controller to lose the shaft positon The posmon error register can hold ±127 steps When an overflow situation occurs, the servo overflow output wifl go to a logic one state and the controller wilt automatically shut off the drive signals to the motor The controller will remain in this state until reset by the host processor

Fig 3 shows a picture of the integrated circuit This 3 48-mm-by-3.3-mm IC dissipates about 100 mW at a clock frequency of 2 MHz. Numerous togic cells are used and most of the random logic is implemented by programmable logic arrays (PLA). This greatly reduces the complexity ot the layout and was one of the prime factors In the speedy turnaround of the design The timing of the logic also maximizes the speed; power tradeoff to achieve low power dissipation.

Acknowledgments

I would like to thank Mike Pan for the excelieni job he did in circuit design and detail checking of the chip Don Hale did the layout. Jerry Erickson did the logic simulation of the circuit and Dave Serisky implemented the CMOS breadboard Special thanks to Mike Lee of hp Laboratories for his advice and encouragement.

Clement C. Lo

Clement Lo was born in Hong Kong ' and attended Ihe University of California at Berkeley where he was awarded the BSEE degree in 1974. Clement then earned the MSEE degree in 1975 from the University of ; California at Los Angeles (UCLA). He came to HP in 1975 and has worked on several ICs for ihe HP-85 A Computer and was project leader for the servo-contrailer chip used in the 4 70OA Clement Is a project manager in the R&D lab at HP's Cor-vallis Division and is a co-author of an article on a prinier-coniroller chip. He is married and lives in Corvallis. Oregon. He enjoys woodworking, gardening, and using small compuiers.

october 19b1 hewle ! 1 packard .journal 9

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