An Enhancement Mode PHEMTfor Single Supply Power Amplifiers

To address the growing handset power amplifier needs for the emerging Personal Communications Services (PCS) markets, a 3-volt, single-supply, enhancement-mode pseudomorphic high-electron-mobility transistor {E-PHEMT} has been developed. The device exhibits + 33-dBm output power and 65% drain efficiency at 1.88 GHz.

. CS telephone handsel manufacturers have hud to face some tough choices to find the most suitable technology for their output power amplifiers. Most manufacturers would prefer to use an amplifier that operates on the 3.0V to 3.6V provided by three nickel-cadmium battery cells or one lithium-ion battery cell.

However, GaAs MESFETs (metal-semiconductor field effect transistors) or PHEMTs (pseudomorphic high-electron-mobility transistors) capable of meeting this need have also required an additional negative voltage supply for proper biasing. Alternatively, a manufacturer could choose a single-supply amplifier using silicon bipolar junction transistors, GaAs heterojunction bipolar transistors, or silicon MOSFETs (metal-oxide-semiconductor field effect transistors). These devices typically require a supply voltage around 4.8V, and to use them the manufacturer would have to raise the battery voltage or use a dc-to-de converter. All of these approaches have efficiency, size, complexity, or cost trade-offs that manufacturers would prefer not to accept if a better device technology were available.

To address this need, an enhancement-mode PHEMT (E-PHEMT) has been developed that provides excellent performance using a single 3V supply. In litis paper, t he original enhancement-mode technology development by HP Laboratories is presented, followed by device development work performed at the HP Communication Semiconductor Solutions Division (CSSD). RF performance results of both a process control monitor device and a 12-mm gate periphery device are discussed, and a comparison of E-PHEMT performance with other device technologies highlights the merits of t his technology. Preliminary device reliability and qualification test results are presented, and test results from a low-cost, plastic packaged, 12-mm gate periphery transistor are discussed.

Development at HP Laboratories

HP Laboratories has been developing an enhancementmode Field effect transistor (EFET) to improve the speed of driver devices in enhancement/depletion-type digital circuitry. This type of device offers two special benefits in handset power amplifier circuitry. Firstly, an EFET only requires positive bias voltage, and can be turned off with zero volts on the gate, but conducts current with positive voltage applied to the gate. Since the drain of a PHEMT is also biased with positive voltage, eliminating the need for negative gate voltage (required for the conventional depletion-mode FET, or DFET) would simplify the operation of the PHE.MT.

Secondly, because of the requirement to deliver maximum current over a small gate voltage swing (- 1 volt), a correctly designed EFET inherently has higher trai is conduct -ance (g[]t), and, more important for class-B power FET

Figure 1

Schematic diagram of the MBE layer structure of the enhancement-mode PHEMT.

Au/Ge/Ni

Au/Pt/Ti

Au/Ge/Ni n* GaAs i" AIGaAs

AIGaAs i InGaAs

AIGnAa/GsAs Super tan ice

GaAs Buffer

AIGaAs

AIGaAs

-— n"

AIGaAs

vr

AIGaAs

Semi-Insulating GaAs operation, bettergm linearity than a conventional DFET. The HP Laboratories' approach employs molecular beam expil axy (MBE) to place a highly doped, thin electron donor layer close to the gate, with the electron donors on hoth sides of the Ino.2Gao.sAs channel. Highly selective reactive ion etching is used to define the vertical position of the Schottky gate. Figure 1 is a schematic diagram of the MBE layer struct ure of the enhancement mode PHEMT.1

Table I summarizes the key characteristics of HP Laboratories' enhancement-mode self-aligned contact (SAC) PHEMT. An important point is that the maximum current ac hieved is no less than that of similarly fabricated depletion-mode PHEMTs, and is far higher than that of typical MESFETs.

Tai] leJ

Key Characteristics of HP Laboratories' E-PHEMT

Parameter

Threshold Voltage

Maximum Trans conductance

Maximum

Drain

Current fT

Unit

Conditions yd-2y

Typical Typical Wafer Wafer Mean

0.06

mA/nmi

GHz GHz

60 120

0.04

57 36

To explore the potential of HP Laboratories' enhancement-mode SAC PHEMT as a handset power device, a large-signal model was extracted from 100-iuu gate width devices. An extensive HP Microwave Design System simulation was performed for both analog and digital handset applications. Table II summarizes the simulated results for both two-tone input (digital modulation) and one-tone input (analog modulation).

February 1998 • The Hewlett-Packard Journal ^^^

Table II

Power Performance of E-Mode SAC PHEMT

Parameter*

Unit

Specification

Simulation Results

2-Tone Power Out

dBm

28.5

28.5

Power-Added Efficiency @ 28.5 dBm

96

>50

53

Gain @ 28.5 dBm

dB

>15

19.6

IM3 @ 28.5 dBm™

dBc

< -26

-40

IM5 @ 28.5 dBm**

dBc

< -36

-37

[email protected] 28.5 dBm**

dBc

< -45

-45

1-Tone Power Out

dBm

31.5

31.5

Power-Added Efficiency @ 31.5 dBm

%

>60

71.6

Gain ® 31.5 dBm

dB

>15

19.5

Quiescent C urre 111

mA

145

Gate Width

nun

8.6

" Imennodutatioti (IM | distortions have been calculated for two tones spaced by 5 kHi at 900 MHi.

" Imennodutatioti (IM | distortions have been calculated for two tones spaced by 5 kHi at 900 MHi.

The very encouraging simulated results prompted the HP Communication Semiconductor Solutions Division fCSSD) to further examine HP Laboratories' enhancement-mode SAC PHEMT. Load-pull measure mentis at 2 GHz performed on 100-itm gate width devices indicated 13.4-dBm (219-mW/mm) power, 191-dB gain and 75.:?% power-added efficiency at Vj = 3 volts. Since these results exceeded the anticipated product specifications by significant margins, a strategy was formulated to make available a first-generation product based on a simpler, nonself-aligned process.

Figure 2 shows the power performance at 2 GHz of 200-utu gate width DFETs and EFETs fabricated at CSSD with a nonself-aiigned process. Although the performance was not as good as IIP Laboratories' self-aligned FETs, the 223-mW/mm saturated power and 66% power-added efficiency exhibited by these devices at V(I = ;! volts are still state-of-the-art Figure 2 also clearly establishes the superior gain and efficiency of EFETs compared to DFETs at low input power.

The power measurements taken on EFETs and DFETs, which are processed the same way, also dispell another concern of employing EFETs for power amplification:

that EFETs will draw unusually large gate leakage current in power saturation. From the load-pull measurements done for the data shown in Figure 2, the quiescent gate leakage current at 3-dB gain compression is positive and < 1 inA for the EFET, and is negative and < 1 mA for the DFET.

With the groundwork at HP Laboratories clarifying the potential of an en ban cement-mode power PHEMT. a project was launched at CSSD and the results from that project are described in the remainder of this article.

Development at CSSD

For the 3-volt, enhancement-mode, high-gain power transistor, one has to investigate candidate devices to determine their potential for low knee (saturation) voltage, high transconductance at low quiescent current, and high current supply capability. High transconductance at low current gives better linearity when the device is operated at low currents in high-linearity applications, and high current capability leads to better power output. The 3-volt operation favors PHEMTs because the PHEMT drain current saturates at very- low voltages ( low knee voltage). This allows greater dynamic voltage sw ing. In addition, the high electron mobility of PHEMTs provides high gain and high current. Pseudomorphic HEMTs are fabricated on GaAs substrates using MBE.

Discrete devices were fabricated with several different MBE material profiles. To evaluate ihese devices, on-wafer small-signal data and load-pull data was collected

Figure 2

Comparison of the power performance of EFETs and DFETs Gates are 200ii m wide and 0.2ii m long. Gates and contacts are not self-aligned to each other.

Comparison of the power performance of EFETs and DFETs Gates are 200ii m wide and 0.2ii m long. Gates and contacts are not self-aligned to each other.

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