## Problems

5-1. In a single stage it is possible to compensate exactly for all time the sag introduced by the cathode circuit alone. Find the value of Rd and Cd to compensate exactly a stage with a cathode circuit comprising Rt and Ck■ Note that both Rd and Cd must be specified for the compensation to be good for all time.

5-2. For an amplifier whose gain function is described by Eq. (5-3), what can be said about the relationship between the sag (expressed as initial slope) and the steady-state low-frequency cutoff frequency? Consider three cases:

b. n arbitrary but known c. n arbitrary but unknown

5-3. (This problem utilizes the results of several of the previous chapters as well as this one.) An amplifier with a gain of 100 db is required. The amplifier is to be made of identical stages (as far as high frequencies are concerned) using 6AK5's. (Assume that the load connected to the last stage has the same capacity as the 6AK5 input capacity.) The 6AK5 characteristics are

Ef = 6.3 volts 1/ = 0.175 amp Cep = 0.02 pf Cin = 4.0 pf Cout =2.8 pf

Assume a total wiring capacitance of 5 pf which is distributed equally between plate and grid circuits.

Typical operation:

Eb = 180 volts Ec2 = 120 volts Ecl = -1.8 volts lb = 7.7 ma

3m = 5,100 jiimhos rp = 0.5 megohm rp2 = 20 kilohms fm

(Note that the parameters change little with moderate changes in E/,.)

a. Assuming two-terminal interstage networks with m = 0.25, what is the minimum over-all rise time?

b. How many stages are required to obtain this minimum rise time?

c. The number of stages found in (b) is excessive; therefore, it is decided to use only 10 stages to obtain the 100-db gain, but to use the four-terminal networks of Fig. 4-9, 4-10, or 4-11. With the network which will give the fastest rise time, what is the over-all rise time of the amplifier? (Note that capacitance must be added to the interstages to preserve the ratio C1/C2 which is required by a given network.)

d. Assume that one sag-compensating circuit will be used for each pair of stages. Let Ck = 200 ¿if; Cs = 1 nU Rg — 1 megohm; and Crc = 0.1 /if. Compute the necessary values for the sag-compensating circuit. For what length of time will the sag be compensated (make only a rough estimate)?

e. Carefully draw the complete schematic diagram for two stages of the amplifier, including the values of all components. Assume that Vbb = 200 volts.

5-4. A complete transistor amplifier is shown in Fig. P5-4. The common-collector stage at the input provides a high input impedance; the common-collector stage at the output provides a low output impedance; and the voltage gain is provided by the

-lOv common-emitter stage in the middle. Assume that rc = 10 ohms, n, = 1 kilohm, rc = 1 megohm, and a — 0.99 for all transistors.

a. What is the over-all voltage gain?

b. What is the value of Cd required to give zero initial sag in the output voltage v0(t)? (Be sure to make all reasonable approximations in the representation and calculation of the circuit.)

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