By Peter Traneus Anderson KCHR
This article describes a simple SSB receiver using the new Harris HSP50016GC-52 Digital Down Converter (DDC).1 The DDC is a complete Weaver-method receiver implemented digitally in one CMOS chip,2-3 A simple SSB receiver using the DDC needs only an RF A/D converter, an audio D/A converter, and a source of configuration bits. When combined with a good A/D and a DSP, the DDC can perform all functions of a modern high-performance HF communications receiver. The present version of the DDC is limited to signals below 26 MHz, but faster versions are promised that will handle signals as high as 38 MHz. Once good A/D converters are available cheaply, a highperformance DDC-based receiver will become much cheaper than an equivalent analog-based receiver.
The simple receiver described here uses a cheap 6-bit flash A/D converter, which limits the receiver to 35-dB dynamic range. This is miserable, but is good enough to demonstrate the DDC's
Notes appear on page 23,
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operation. A better A/D can easily be substituted, with a corresponding improvement in performance.
To fully use the DDC's capabilities, an A/D giving 16 bits or better linearity at 52 megasamples per second (MSPS) is required. If you have one of these in your junk box, feel free to use it.
The DDC's performance specifications are not modest:
• Clock frequency 0 to 52 MHz
• Input signal frequency zero to one half the clock frequency
• Spurious free dynamic range (SFDR) 102 dB
• Passband (-3 dB) to stop-band (-102 dB) shape factor 1.5
• Passband width variable over a wide range
• Output passband center frequency fixed at 1.79 times the passband width in real-output mode
• Output passband center frequency fixed at zero in quadrature-output mode
Direct Digital Synthesizer
Direct Digital Synthesizer a-
Audio Output Serial 32 Bits
Fig 1—Bloek diagram of the Harris HSP50G16 Digital Down Converter. This is a complete Weaver-method receiver in one digital »hip.
• External DSP can easily shift output passband center frequency
• $160 in 48-pin pin-grid array (PGA) package 4
• Cheaper in 44-pin plastic leaded chip carrier (PLCC) package
Fig 1 shows the block diagram of the HSP50016. This is a classic Weaver-method receiver. The frequency of the first synthesizer (often called the local oscillator) and the passband of the low-pass filters are programmable. The frequency of the second synthesizer (sometimes called the Weaver oscillator) is fixed at 1.79 times the filter cutoff frequency.
The term "decimating" refers to the fact that the output sample rate is a fraction of the input sample rate.
The second mixers, second synthesizer and final adder can be bypassed, and their functions implemented in an external DSP. The DSP can then vary the frequency of the second synthesizer independent of the filter passband, thus shifting the audio passband without varying its width.
The combination of programmable bandwidth and programmable passband shift permits the upper and lower audio passband edges to be set independently. There will be some stopband aliasing around zero frequency if the lower passband edge is set too low. Additional filtering in the DSP can eliminate this aliasing.
In effect, the addition of a DSP would give the receiver a large collection of bandpass filters of various center frequencies and passband widths, with a constant shape factor of 1.5. Note that even very narrow filters used for CW would have the good
shape factor. This does not occur with analog crystal filters.
For the receiver described here, I opted for simplicity rather than flexibility, and did not use a DSP.
I strongly recommend that anyone building this receiver obtain a copy of the HSP50016 data sheet. Curiously, the data sheet makes no mention of Weaver or his method. Those who wrote the data sheet wrote mostly in terms of complex exponentials rather than in terms of sines and cosines.
The implementation of the second mixers, second synthesizer and final adder is called "quadrature-to-real conversion." The math for these functions is derived in the data sheet. These operations reduce to little more than a four-input multiplexer in the actual implementation.
The DDC requires 320 bits, contained in eight control words of forty bits each, to fully set up its configuration. I do not have the space to describe all these bits, so will describe only the minimum to use this specific receiver design. The data sheet is very complete and will reward thorough study. The information is all there, though not always where it might be expected.
Fig 2 shows the block diagram of the simple receiver. The signal from the antenna goes first through a variable attenuator and then through a tunable bandpass filter. These sections reduce the spurious responses due to the poor dynamic range of the 6-bit A/D converter. A broadband amplifier with a gain of 44 dB amplifies weak signals for application to the A/D converter.
A high-brightness light-emitting diode (LED) connected to the A/D over flow output glows whenever the A/D input signal exceeds the positive limit of the A/D. The LED is a high-brightness type so that even occasional overflows will cause visible flickering of the LED.
A 25-MHz clock drives both the A/D and the DDC. All of the outputs from the DDC are derived from this clock.
The DDC output serial bit stream is applied to the 16-bit D/A converter.
The digital gain setter provides numerical gain by shifting the data-bit timing of the D/A converter, implicitly using the serial bit stream as a variable-length shift register. For this function to work the D/A must have a two's-complement input rather than an offset-binary input.
The output of the D/A converter is lowpass filtered in a switched-capacitor filter. This filter is clocked by the same clock used to shift data into the D/A. Thus, the filter cutoff frequency (which is 1/100 of the filter clock frequency) is controllable from the DDC. When the clock is 38 times the D/A sample rate, the filter cutoff frequency is the same as the high passband edge in the DDC.
The filter output passes through a fixed analog low-pass filter and an audio amplifier to the headphones or speaker.
The printer-port interface provides control bits to the receiver. This port looks just like a parallel printer to the computer. Thus, the receiver is programmed by "printing" text strings from the computer. The data format is chosen so that no assembly-language programming is needed: control characters and lowercase characters are
CDATA ^ CSTB
CDATA ^ CSTB
Fig 3—PC printer-port interface.
Fig 3—PC printer-port interface.
ignored. Uppercase characters program the digital gain setter, and numeric characters program the DDC.
Fig 3 shows the details of the printer-port interface. Look in the manual to a Centronics-compatible printer to see the interface this circuit is imitating.
All signals to or from the printer are buffered in Ul. U1 protects the rest of the receiver from transients coming in the printer connector. For this reason, I socketed Ul.
Only four of the eight data bits are used, just enough to perform the required functions. A fifth data bit is buffered, for future expansion.
U3, U4 and the associated parts gen-eratejhe ACK and BUSY outputs from the STB input pulse. STB idles high, and pulses low once for each character. The data lines stabilize before STB goes low and remain stable after stb goes high. The rising edge of stb clocks the data into the DDC or the gain setter.
U2 contains two two-to-four decoders. One decoder is used to determine whether the character is a control, numeric, uppercase, or lowercase character. If the character is a control character (00 to IF hex), U2 pin 4 pulses low. Control characters are ignored. If the character is a lowercase character (60 to 7F hex), U2 pin 7 pulses low. Lowercase characters are ignored. If the character is a numeric character (20 to 3F hex), U2 pin 5 pulses low, and the two lowest data bits are clocked into the DDC control port on the rising edge of the pulse. If the character is an uppercase character (40 to 5F hex), U2 pin 6 goes low, and the second decoder in U2 decodes the two low data bits.
If the character is U2 pin 12 pulses low, resetting the DDC.
If the character is "A," U2 pin 11 pul ses low, resetting the gain setter to minimum gain.
If the character is "B," U2 pin 10 pulses low, reducing the gain setting of the gain setter.
If the character is "C," U2 pin 9 pulses low, increasing the gain setting of the gain setter.
The DDC contains eight forty-bit control words, numbered zero through seven. The first three bits of each control word are the address of that control word. The control words are sent most-significant bit first. Words zero and seven are not used here.
To program one control word, the computer sends a forty-one digit number consisting of the character "2" followed by forty characters "1" or "0." The "2" tells the DDC that the next forty digits are data for a control word. Each "1" or "0" places a one or zero bit into the control word. Control characters or lowercase characters may be placed between digits if desired, to improve human readability.
For initial testing, I programmed the receiver by using a text editor to print blocks of text. Table 1 gives the text.
Print the block from "start-initialization" to "end-initialization" to initialize the receiver. The first two lines are comments and need not be printed. These lines contain only lowercase and control characters, so they do no harm if printed. Note that the tilde (~) is a lowercase character.
The third line prints two characters:
to reset the DDC, and "A" to reset the gain setter to minimum gain.
The fourth line programs control word two, and the fifth line programs control word three. These words control frequency-chirp features which are not used here.
The sixth line programs control word four. This word sets the output to real mode, sets internal scaling, and sets whether the output is spectrally reversed. The last bit in the word is 0 for nonreversed spectrum, for upper-sideband (USB) reception. The last bit is 1 for reversed spectrum, for lower-sideband (LSB) reception. The word is shown for LSB, as that is the usual case on 75 and 40 meters.
The seventh line programs control word five. This word sets up the passband width, internal scaling, and output format. The formats available are 16, 32, or 38-bit fixed point, or 32-bit IEEE floating point. The fixed-point formats can be two's complement, offset binary, or sign-magnitude format. The serial output can be most-significant bit first, or least-significant bit first. This receiver uses 32-bit fixed point, two's complement format, output most-significant bit first.
For this receiver, the audio passband is set to pass frequencies between 770 Hz and 2730 Hz. This gives tinny, but very intelligible, sound.
The eighth line programs control word six. This word sets the IQCLK rate and polarity, the IQSTB location and polarity, and the output data polarity. This receiver uses IQCLK running continuously at 38 times the D/A sample rate, with data stable on the falling edge of IQCLK. IQSTB is set to be high during data output, and low otherwise.
Control word six also selects the input data format to be two's complement or offset binary. This receiver uses offset binary to match the A/D output format.
The ninth line is a comment, and has no effect on the receiver.
The tenth line programs control word one. This word sets the phase increment and also is used to make all the previous words actually take effect. The phase increment is initialized for reception of WWV on 5 MHz.
The eleventh line is a comment, and has no effect on the receiver.
The phase increment word (control word one) sets the frequency the receiver is tuned to. Once the receiver is initialized, the frequency can be changed by printing a phase incre-
Fig 4—Bandpass filter and A/D converter.
ment word with a different phase increment setting.
The bottom five lines of Table 1, which are not part of the programming strings, show how to calculate the phase increment for any frequency between zero and half the clock frequency. Fcarrier is the conventional carrier frequency of the SSB or AM signal being received. FLO is the local oscillator frequency. FCLK is the clock frequency from the A/D.
As in any Weaver-method receiver, FLO is offset from Fcarrier. For this receiver, the offset is 1.75 kHz. For LSB, the offset is subtracted from the carrier frequency. For USB, the offset is added to the carrier frequency.
The phase increment is a 32-bit binary integer describing how much the phase of the local oscillator advances at each pulse of the clock and equals two raised to the thirty-third power, times the ratio of FLO to FCLK.
The phase increment is converted to hexadecimal with a pocket calculator, and then each hexadecimal digit is manually converted to binary. A tilde is inserted every four bits to facilitate this manual conversion. The bits are printed MSB first, which is the usual order of printing the digits of a number on a printout.
The phase increment takes up 32 of the 40 bits in control word one. The first three bits of the word are the word address, and the next bit tells the DDC to make the word take effect. The last four bits set the local oscillator for CW (fixed-frequency) mode, rather than a chirp (swept) mode.
The chirp modes would be handy for band scanning, except there is no obvious way to stop a sweep on a particular CW frequency.
Fig 4 shows the weak spot of this receiver: the RF input circuitry and the A/D converter. If you have a better A/D, use it. Any A/D with offset-binary TTL-level outputs at 25 MSPS may be used without changing the control words. Any A/D with outputs up to 52 MSPS may be used if the control words are changed accordingly.
U12 is a 50-MHz clock oscillator, chosen for low cost rather than for low phase noise. The power to the oscillator and A/D is filtered to reduce noise from other logic.
U13 divides the oscillator frequency by two, and provides two complementary outputs, one for the DDC and the other for the A/D. The DDC expects the data to be stable on the rising edge of the clock to the DDC. The A/D used here provides stable data on the falling edge of the clock to the A/D.
U14 is a CMOS six-bit flash A/D converter, Micro-Networks advertises the MN5906 to be a 50-MHz converter, but guarantees only 35-MHz performance. The converter is used here at a conservative 25 MHz.
U14 is supplied with a reference voltage of about 2.6 V from a 2N3904 emitter follower. U14's reference input appears as a 90-Q resistor to ground.
1)8 Harris HSP50016GC-52
1)8 Harris HSP50016GC-52
Fig 5—HSP50016GC-52 f 1 2 3 6 7 8
connections. (_Dot On Top Side
Indicates Pin A1
Table 1: Text blocks to print to receiver start-initialization reset~set~to~min~gain~set~to-lsb~mode @A
20100000000000000000000000000000000000000 20110000000000000000000000000000000000000 21000000010000000000000000000000000101001 21010000011011111001111111011100011100101 21100000000011101010100100100000001100110 phase~increment~word~for~wwv~five~megahertz~frequency 20011-0110-0110-0101-1101-0011-1001-1001-0111-0001 end-initialization gain-settings minimum~A decrease~B increase~C
phase increment calculation: FLO = Fcarrier - 1.75 kHz FCLK = 25000 kHz
32bits~phase~increment = (2A33/FCLK)*FLO 20011 <32bits~phase~increment>0001
U3 74LS14 11K. 10
Fig 6—Digital gain setter.
DACCLK To U9, U10
CLEAR 2ND RC
CLEAR GND RC
The signal input to U14 is ac-coupled. Two 10-k£2 resistors bias the input at midscale. Two germanium diodes protect the input from spikes outside the A/D's supply and ground rails.
A high-brightness LED provides overflow indication.
The RF input signal passes first through a variable attenuator comprising a 5000-£2 audio-taper potentiometer and a 47-i2 fixed resistor. Note that the pot is wired so that the usual maximum-volume setting is actually the maximum-attenuation setting.
The signal then passes through a double-tuned preselector. The variable capacitor is a receiving type with two identical 400-pF sections.
U15 and associated parts provide about 44 dB of ac-coupled gain, with enough output swing to drive the A/D.
The six output bits of the A/D drive the six most significant input bits of the DDC. The remaining ten input bits of the DDC are grounded.
Fig 5 shows the pinout of the HSP50016GC-52 DDC. This is the 48-pin pin-grid array (PGA) package. Change the G in the part number to a J for the cheaper 44-lead plastic leaded chip carrier (PLCC) package. I used the PGA package because the PLCC was not then available. The PLCC should be available now.
I built the receiver dead-bug style on copper-clad board to provide a good ground plane. The 50016 is clamped to the copper to provide the necessary heatsinking.
Fig 6 shows the gain setter. A fourbit up/down counter, U5, holds the gain setting programmed by the computer, and provides sixteen possible gain settings.
The DDC is programmed to give approximately 38 IQCLK pulses per D/A sample. The DDC serial data is programmed to be 32 bits. IQSTB is programmed to be high during the 32 data bit times and low during the approximately 6 remaining bit times.
The D/A needs a latch enable (LE) pulse at the end of a 16-bit data word. The gain is varied by varying which 16 bits (out of the 32 bits from the DDC) is loaded into the D/A. This is accomplished by varying the delay from the rising edge of IQSTB to the LE pulse.
The gain is minimum when the first sixteen bits are used, as the data is sent MSB first. As the delay is increased, lower-significant bits are used, increasing the gain at 6-dB per step.
This function relies on the fact that, in a two's-complement integer ex-
pressing a small number, the highorder bits are either all zeros or all ones, depending on the sign of the integer.
U6 and U7 comprise an eight-bit fully synchronous up counter. When IQSTB is low, U6 and U7 are loaded with a count corresponding to the desired gain setting.
When IQSTB goes high, U6 and U7 count up to their highest count, all ones, then count once more, and halt until IQSTB goes low again. U7 pin 15 is high only when the counter is at its highest count.
NAND gate U4, pins 4, 5 and 6, converts the pulse from U7 pin 15 to the LE pulse for the D/A.
Fig 7 shows the D/A converter, low-pass filter, and audio power amplifier. U9 is a 16-bit serial-input D/A converter of the type used in digital audio players. This is a single D/A, rather than the usual dual D/A. The D/A full-scale output is plus or minus 3-V peak.
U10 is a switched-capacitor low-pass filter with a clock to passband corner frequency ratio of 100, and a passband-to-stopband shape factor of 1.2 at 58 dB down. IQCLK is set so that the corner frequency is the same as the high passband edge from the DDC.
The uncommitted op amp in U10 is used as a low-pass filter to remove clock noise from UlO's output.
Ull is an audio power amplifier used to drive headphones or a small speaker. The inband gain from the D/A output to the phones is about 6 dB.
To operate the receiver, the receiver is initialized from the computer, the desired phase increment is printed from the computer, and the preselector is set to peak the signal.
The RF attenuator should be set so that the overflow LED just barely flickers. If the signal is too loud in the phones, increase the RF attenuation. If the signal is too soft, increase the digital gain setting.
The strongest AM broadcast station in your area makes a good test signal as it is usually strong enough to get through the preselector with the capacitors set to maximum capacitance.
This receiver has lots of room for improvement, but is good enough to demonstrate the HSP50016, and the great job done by the 50016's designers.
As A/D converters improve in cost and performance, we will see expensive analog high-performance communications receivers replaced by cheap, flexible digital receivers.
This is both exciting and sad. Receivers will become better and cheaper, but the designs will become more inaccessible to those who wish to learn how they work.
1 Harris Semiconductor, 1301 Wood Burke Road, Melbourne, FL, 32902, 407 7243000.
2Weaver, D. K., "A Third Method of Generation and Detection of Single-Sideband Signals," Proceedings of the IRE, Dec 1956. 3Anderson, P. T., "A Different Weave of SSB
Receiver," QEX, Sep 1993, pp 3-7. 4Available from: Gerber Electronics, 128 Carnegie Row, Norwood, MA 02062, 617 769-6000. DO
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