By Peter Traneus Anderson KCHR

This article describes two upgrades to my simple SSB receiver using a digital down-converter (DDC): an improved analog front end and A/D converter and a simple control program.1 The improved front end increases the nominal dynamic range from 36 dB to 60 dB. The control program permits tuning the receiver from the keyboard of a PC.

As before, this is intended as a starting point for further improvements and to encourage experimentation with new technology.

Fig 1 shows the improved band-pass filter and A/D converter. This circuitry replaces Fig 4 in Note 1. The input signal passes through a variable bandpass filter and a two-stage amplifier to the A/D converter. The A/D output is applied to the DDC input.

The signal strengths at my antenna are low enough so that the increased dynamic range of the new A/D eliminates, for me, the need for an input

1 Notes appear on page 15.

990 Pine Street

Burlington, VT 05401

email: [email protected](lnternet)

attenuator. In strong-signal areas, an attenuator will still be needed.

The band-pass filter includes coils LI and L2 and a dual 400-pF variable capacitor. Plug-in coils LI and L2 are inductively coupled. The frequency range covered is changed by changing the values of LI and L2.

Fig 2 shows LI and L2 for three bands: 0.55 to 1.6 MHz, 3.4 to 11 MHz and 14 to 22 MHz.

The first band provides coverage of the AM broadcast band. This is useful for testing and demonstrations, as stable signals are always available.

The second band provides coverage of the 80, 40 and 30-meter amateur bands, as well as the 49, 41 and 31-meter shortwave broadcast bands.

The third band provides coverage of the 20, 17 and 15-meter amateur bands. The signal frequency is between one-half and one times the A/D clock frequency. This results in the signals being aliased down to frequencies between zero and one-half of the clock frequency. The effect is identical to what would happen if a mixer were placed between the band-pass filter and the A/D input, with the mixer's LO port being driven by the A/D clock frequency. A signal appears to the DDC

to be at a frequency equal to the clock frequency minus the signal frequency , and the sidebands are swapped. Thus, an upper sideband (USB) signal at 21.3 MHz appears to the DDC as a lower sideband (LSB) signal at (25 MHz-21.3 MHz) = 3.7 MHz. A USB signal at 14 MHz appears to the DDC as an LSB signal at (25 MHz-14 MHz) = 11 MHz.

For the 0.55 to 1.6-MHz band, LI is omitted. A loop antenna from an old AM radio is used for L2. Strong local stations will overload the A/D. Detuning the variable capacitor or orienting the loop to put a null in the direction of the strong station will eliminate the overload.

I added a two-turn link, connected between the antenna-input terminal of LI and the ground terminal of L2, to permit using an external antenna for weak stations.

For the 3.4 to 11-MHz band, LI and L2 are each a pair of 3.3 |iH, axial-lead miniature molded RF chokes in series. The two chokes in LI are aligned axially, as are the two chokes in L2. The two pairs of chokes are placed close together with the choke bodies touching to provide coupling from LI to L2.

Inverter Lm733

To 50016 DDC

100 il H

Signai Processing Technologies SPT7855SCS

100 il H

Signai Processing Technologies SPT7855SCS

To 50016 DDC

rrrrx^

w rrrrx^

Fig 1—Improved band-pass filter and A/D converter. This circuitry replaces Fig 4 in Note 1. The filter is sharper due to looser coupling. See Fig 2 for values of plug-in coils L1 and L2. The A/D converter is upgraded to 10 bits.

12 QEX

For the 14 to 22-MHz band, LI and L2 are each a pair of 3.3 |iH axial-lead miniature molded RF chokes in parallel. The four chokes are placed close together with choke bodies touching to provide coupling from LI to L2.

The two-stage preamplifier provides a gain of 55. The gain is reduced from the previous design to keep the input voltage corresponding to one count in the A/D roughly the same as before.

The first stage, U16, is an LM733 IC RF amplifier run with all gain pins open, to give a gain of 5. The 733 is an old, cheap, readily available 90-MHz bandwidth differential preamplifier.

The second stage, U15, an HFA1130P from Harris Semiconductor, is a high-speed current-mode operational amplifier (op amp) config ured for an ac gain of 11 and a dc gain of unity.2

In a conventional (voltage-mode) op amp, the output voltage is proportional to the voltage difference between the noninverting input and the inverting input. Both inputs have high impedance and draw very little current. The output drives an external feedback network to maintain the voltage difference between the two inputs at zero.

In a current-mode op amp, the noninverting input is a high-impedance input that drives an ideal emitter follower. This follower is made using NPN and PNP transistors so it can provide output currents of either polarity, with zero base-to-emitter voltage drop.

The output of the emitter follower is actually the inverting input. Thus, the emitter follower forces the inverting-input voltage to be equal to the voltage on the noninverting input. The current needed to do this forcing comes from the collector of the emitter follower. The collector current is forced to flow through a capacitor internal to the op amp. The voltage across this capacitor is buffered by another ideal emitter follower to provide the op-amp output. The output drives an external feedback network to maintain the inverting input current at zero.

The current-mode op amp used here provides two advantages over a voltage-mode op amp: more gain at high frequencies and output voltage clamping.

Voltage-mode op amps exhibit constant gain-bandwidth. The product of the closed-loop gain and the closed-loop bandwidth is a constant. Thus, if you want more gain, you must accept less bandwidth.

Current-mode op amps exhibit constant bandwidth. The closed-loop bandwidth is roughly constant, independent of the closed-loop gain. Thus, the gain-bandwidth increases as the closed-loop gain increases, within limits. The bandwidth does vary with the resistance of the feedback resistor. (See the HFA1130 spec sheet for details.)

The voltage-clamping feature is set by the wiring of pins 8 (+limit) and 5 (-limit) to keep U15's output voltage between ground and +5 V. This is necessary, as the CMOS A/D can be damaged by input voltages below ground.

U17, an AD780AN from Analog Devices, provides a stable 3-V reference for the A/D converter.3 The full-scale range of the A/D analog input extends from zero to the reference voltage. A pair of resistors sets the dc operating point of the preamplifier output to be half-scale of the A/D input.

Oscillator U12 and flip-flop U13 provide a stable 25-MHz square-wave clock to the A/D and the DDC. Both the A/D and the DDC respond to the rising edge of the clock.

The 10-bit A/D converter, U14, is a SPT7855SCS from Signal Processing Technologies.4 This is a 25-mega-sample-per-second (MSPS) CMOS A/D. Internally, it is 16 matched 10-bit succesive-approximation A/Ds running in time-staggered fashion. Each internal A/D converts one input sample every 16 clocks. Overall, one sample is converted during each clock,

3.3 flH

3.3 flH

3.3 fiH

Fig 2—L1 and L2 for three bands: 0.55 to 1.6 MHz, 3.4 to 11 MHz and 14 to 22 MHz. The highest band drives one of the alias responses of the A/D to provide USB reception instead of LSB reception.

ARRL Lab Tests of the DDC-Based Receiver

ARRL Laboratory Engineer Mike Gruber, WA1SVF, tested the improved receiver in the ARRL Lab, while I assisted by operating the receiver.

All of the tests were performed with the receiver set for 400-Hz bandwidth, using the 10-bit A/D converter. The results follow: Minimum Detectable Signal (MDS): At 3.520 MHz, MDS = -129 dBm At 14.020 MHz, MDS = -105 dBm At 21.020 MHz, MDS = -129 dBm Because the MDS was unexpectedly higher at 14 MHz, we did not perform the other tests at 14 MHz. Third-Order Intermodulation Distortion Dynamic Range (IMDDR): At 3.520 MHz, IMDDR = 57 dB At 21.020 MHz, IMDDR = 70 dB

Because the A/D is only 10 bits linear, I expected about 60-dB IMDDR. We measured IMDDR a second time at 21 MHz. The band-pass filter tuning sometimes affected 21-MHz IMDDR and sometimes didn't. The second measurement at 21 MHz gave 73 dB. Blocking Dynamic Range (BDR): At 3.520 MHz, BDR = 91 dB At 21.020 MHz, BDR = 91 dB The BDR was limited by overflow in the A/D.

#include <stdio.h> #include <atdlib,h> #include <string.h>

/* PC control program for 50016 receiver & 25 MHz */ /* 20aug94 PTAnderson KClHR */

char postamblet] = "000 01";

char ph_inc_string[} * "20011011001100101110101010001011110010001";

long maxfreq = 12000000;

long freq = 5000000;

float tempfloat;

double dfreq;

double dsfreq;

double dafreq;

double dph_inc;

long ph_inc;

double fclock = 25000000.0; double two..up32 .over__fclock;

two_up32_over..fclock = 4294967296.0 / fclock;

/* initialize receiver to minimum gain */ fprint f(stdprn,"@A\n");

/* initialize control registers 2 and 3 (same data for SSB or CW) */ fprintf <stdprn,"20100000000000000000000000000000000000000\n") ; fprintf(stdprn,"20110000000QOOOOOOOOOOOOOOOOGOOOOOOOOOOOO\n");

printf("\nSimple SSB receiver set for lower sideband reception");

printf("\n\ncenter of rf passband a frequency - 1.75 kHz");

printf("\n\nexit to DOS: aet DDC clock kHz: set frequency kHz:");

printf("\n\nup frequency:");

fprintf(stdprn,"2100000001000000000000000000000000010100l\n");

fprintf(stdprn,"210100000110lllll001111111011100D11100i01\n">;

fprintf(stdprn,"21100000000011101010100100100000001011010\n");

break;

fprintf(stdprn,"2100000001000000000000000000000000001001i\n"); fprintf(stdprn,"2101001000l011100000101001100110100100l01\n">; fprintf(stdprn,"21100000000011101010100100100000111001000\n"); break;

case 'e

1000

5000

printf("\n\n q=1MHz w=10QkHz e=10kHz r»5kHz t=lkH2 y=100Hz uslOHz i=lHz"); freq = freq ♦ 10000

printf("\n\ndown frequency:"); printf("\n\n a^lMHz a=100kHz d=10kHz f=5kHz g=lkHz h=100Hz j=10Hz k=lHz"); printf("\n\ngain; bandwidth Hz:");

printf("\n\n z=up x=dn c=min n=2000 m=400");

printf("\n\nlaBt command, gain, alias, frequency in kHz now are:\n\n");

/* up 100kHz dn 100kHz

gain_state = gain_state + 1; fprintf(stdprn,"C");

else

gain_state = gain_state - 1; fprintf(stdprn,"B");

break ;

case 'c': gain_state = 0; fprintf(stdprn,"A"); break;

case '=': printf("\rfreq kHz "); cscanf( "%t", fctempfioat ); freq = 1000.0 * tempfloat; tempint = getch(); break;

case '#': /* set fclock in kHz printf("\rclock kHz "); cscanf( "%f", &tempfloat ); fclock = 1000,0 * tempfloat; two_up32_over_fclock = 4294967296.0 / fclock; tempint = getch();

break;

break;

default: break;

freq = 10000; dfreq = freq; dsfreq = 0.001*dfreq; dafreq = 0.001*(fclock-dfreq); dph_inc = (dfreq-1750) * two_up32_over_fclock; ph_inc = dph_inc; dph .inc s ph__inc; printf("\r%c %2.2u %9.3f %9.3f dsfreq) ,-

Btrcpy( ph._inc_string, preamble );

ph_inc = ph._inc << 1; if( ph_inc < 0 ) strcat( ph_inc_atring, "1" ); else strcat( ph_inc_string, "0" ); }

strcat( ph._inc_string, poatamble ); for( j»0; j < 41; j = J + 1 ) i fprintf(stdprn,"%c", ph_inc_string[j]);

c, gain_atate, dafreq,

14 QEX

»-Fig 3—Software listing of the control program. This program was compiled in Microsoft Quick C. Other C compilers should work with few or no changes.

but the data appears 16 clocks after the input is sampled.

The 10 data bits from the A/D go to the high 10 bits of the DDC data input. The low 6 bits of the DDC data input remain grounded.

The overrange output of the A/D is buffered by a spare inverter to drive a high-brightness LED. The LED is on when the A/D overflows. The A/D overflows a lot less than the old 6-bit A/D did.

Analog Devices has just introduced a 12-bit, 30 MSPS A/D, the AD9026, costing $238 in thousand quantity.3'5 Unlike some older 12-bit high-speed A/Ds, this A/D is specified to show good linearity at full speed, giving 72 dB of dynamic range. This A/D has a full-scale input range of-1 V to +1 V, so level shifting and input clamping are not needed. A gain-of-nine amplifier, ac-coupled to the A/D input, should work fine with the band-pass filter and square-wave clock of Fig 1.

Fig 3 is a listing of a simple program to control the receiver. It is written in C. I used Microsoft Quick C, version 2.5. Other C compilers should work with few or no changes. Any differences will most likely be found in the library input and output functions.

The program provides commands to increment and decrement the operating frequency by various amounts, to directly enter the frequency, to raise and lower the gain and to change the bandwidth to 2000 or 400 Hz.

The program starts by declaring and initializing variables, then initializes the receiver, prints out a command list and enters the main loop.

The commands are all single characters. The current command character is initialized to 'n,' which means "set bandwidth to 2000 Hz." In the main loop, the current command character is compared to each of the valid commands and the appropriate command, if any, is executed. Thus, the first command executed is to set the bandwidth to 2000 Hz.

After executing a command, the program recalculates the current frequency in kilohertz, the new alias in kilohertz and the new phase increment. The phase increment is calculated as a 31-bit integer, as a long integer is 31 bits plus sign.

The program then prints out the current command character, gain setting, alias and frequency.

Next, the phase increment is converted to the 41-character string format needed by the receiver: a 5-character preamble, 31-character phase increment (most-significant bit first) and a five-character postamble.

The phase increment is converted to characters by left-shifting each bit into the sign bit. The sign bit is then tested to determine if the character should be 1 or 0. Another 0 is included in the postamble to provide the 32nd (least-significant) bit of the phase increment needed by the DDC.

The 41-character string is then sent to the receiver, followed by a newline character string (carriage return and line feed).

Lastly, the program waits for a new command character to be typed before returning to the start of the loop.

As with the hardware, this program is intended as a starting point to be improved upon.

I wish to thank Gil Gianetti, N1FEB, for his support and assistance in the development of this receiver.

Notes

Anderson, P. T., "A Simple SSB Receiver Using a Digital Down Converter," OEX, Mar 1994, pp 3-7. 2Harris Semiconductor, 1301 Woody Burke Road, Melbourne, FL 32902, tel: 407-7243000.

Analog Devices, One Technology Way, PO Box 9106, Norwood, MA 02062-9106, tel: 617-329-4700. 4Signal Processing Technologies, 4755 Forge Road, Colorado Springs, CO 80907, tel: 719-528-2300. 5Wirbel, L., "Tl rolls DSP for cellular; ADI offers converters," Electronic Engineering Times, July 18, 1994, p 83. m

CC-1 Capacitor Kit contains 365 pieces, Ssa ol every 10% value from Ipf to 33^f CR-1 Resistor Kit contains l540pieces, 10ea of every value from lOOso lömegfl Sizes ara 08DS and 1206 Each kit is ONLY $4995 and available tor Immediate One Day Delivery

Order by toll-free phone, FAX, or mail We accept VISA, MC, COD, or Pre paid orders. Company PO's accepted with approved credit. Call for free detailed brochure.

CC-1 Capacitor Kit contains 365 pieces, Ssa ol every 10% value from Ipf to 33^f CR-1 Resistor Kit contains l540pieces, 10ea of every value from lOOso lömegfl Sizes ara 08DS and 1206 Each kit is ONLY $4995 and available tor Immediate One Day Delivery

Order by toll-free phone, FAX, or mail We accept VISA, MC, COD, or Pre paid orders. Company PO's accepted with approved credit. Call for free detailed brochure.

„ mm COMMUNICATIONS SPECIALISTS, INC.

WmmmtM 426 West Taft Ave • Orange, CA 92665-4296 mmtrnrn Local (714! 993-3021 - FAX (714) 974.3420

Entire USA 1-800-854-0547

DOWN EAST MICROWAVE

Was this article helpful?

0 0

Post a comment