L = low)
The table shows that the output of this gate is high (11) only if both inputs are low (L). Any other input combinations result in a L output. We have chosen the NAND gate for this example because this is the gate used in the Micro-1 hi ma tic, Note that if we permanently connect one input to L, the gate becomes an inverter, whose output is always the complement (or inverse) of its input, "his connection eliminates the last two rows of the truth table, Phe remaining two rows show B and Q to be in inverse relationship. By combining NAND gates, complex systems can be formed; in fact, an entire computer can be built from combinations of this logic block.
If one of the inputs to Fig, 1(a) changes, the output may change. The time required or this change is considered to be zero in theory. Thus the NAND gate does not possess memory, The memory or storage function is performed by a flip-flop, We will restrict our discussion to the type of FF used in the keyer Its functional diagram is in Fig, 1(h). The FF lias two outputs, Q and Q. Q is simply the complement of Q. If one is high, the other is low. Q is the nominal output of the flip-flop; Q is the inverted output. In the keyer analysis which follows, when we speak of the state of the FF, we mean the state of Q. Input pulses from a clock or other sources are normally applied to the T (trigger) terminal. The state of Q after the
*The purist would iiLs*p point out that this is the truth table of « NOK irate or a NAND gate. We will not jio into I hat here.
SPEEOT I/a BB3M2B GATE
Fig. 4. Schematic of the pulse generator
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