Output

C9 'MP. OUTPUT

Figure I „ Po wer supply sc hen unie dlug mm,

Figure 4, Rear panel layout*

pull-down of the v)J terminal. In operation, as the supply current rises, sn does the transistor's base-emitter voltage. As it approaches 0.7 volts, the transistor begins to conduct and begins pulling down on the \DJ terminal. The power supply output current remains essentially constant under limit-control even though the output voltage decreases as adj is pulled down.

For my power supply+1 selected a horizontal, open-case, TV-type current-limit adjust pot, mounted flat on ihe circuit board. However, you could mount a pat with a shaft on the power supply s front panel for accessibility.

Another feature of the supply e^ reverse bias protection for the regulator ICs, accomplished by diodes D2 and D4+ Most solid state regulators require the input voltage io remain higher lhan the output voltage as long as power is applied. Under normal conditions, this is fine. However, under some operating conditions, the supply power could accidentally he terminated, causing the regulator's input voltage to tall lasier (to a lower Vilue) than the output voltage.

Thi\ might occur when large value capacitors or NiCd batteries are attached to the supply's output terminals. A lew moments alter power loss, the regulator could be subjected loa reverse bias, resulting in internal

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Figit ri> 2. Winng diagram

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